1. Field of the Invention
This invention relates to computing systems, and more particularly, to synchronizing asynchronous input signals with high reliability.
2. Description of the Relevant Art
Integrated circuits (ICs) use one or more clocks to synchronize work in a pipelined fashion. Sequential elements, such as latches and flip-flops, receive a data input signal and a clock signal. These sequential elements are used throughout the die of one or more cores to provide synchronized processing of control and data signals. These sequential elements have an associated overhead including a setup time and a hold time.
The setup time is a minimum duration of time prior to a sequential element opening for the data input signal to remain stable. The hold time is a minimum duration of time after the sequential element closes for the data input signal to remain stable. If the setup time is violated, then the data input value may not be stored. If the hold time is violated, then the data input value may be overwritten early. When either the setup or the hold time is violated, the signals within the sequential element and an associated data output line become metastable, or unpredictable. Even if the output value settles to a correct value, more power is consumed by both the sequential element and subsequent combinatorial logic. Additionally, the subsequent combinatorial logic takes more time to perform computations. Further, the subsequent combinatorial logic may provide a wrong result if the output value of the sequential element does not settle to a correct value. The parameter Mean Time Between Failures, or MTBF, indicates an average time interval between two successive failures of a particular element on a chip.
Although an IC design may include timing paths and combinatorial logic between sequential elements to satisfy setup and hold times, violations of setup and hold times may still exist. For example, the sequential elements may receive asynchronous signals. One source of asynchronous signals occurs when synchronous data and control signals are exchanged between different clock domains. The different clock domains may use different clock frequencies. Alternatively, the different clock domains may use a same clock frequency but use an arbitrary phase relation between the clock signals.
System designers include circuitry, such as synchronizers, to minimize metastability. The synchronizers are located at interfaces and include scan input logic, reset or clear logic, recycle stored data capability, gated clock capability, and so forth. This added functionality may decrease the MTBF of the flip-flop, which increases a number of failures and decreases system reliability.
In view of the above, efficient methods and mechanisms for synchronizing asynchronous input signals with high reliability are desired.